SDRAM memories were developed to adapt to the ever increasing operating speed of processing circuits of the microprocessor type. While standard DRAM memories have a transfer frequency limited to a few tens of megahertz, architectures with SDRAM memories can achieve operating frequencies of 100 MHz or more.
SDRAM memories utilize a synchronous interface circuit where all the signals are sampled on the same clock edge. These signals are, for example, the address and data signals, the control and instruction signals such as "cs", "ras", "cas", "we", "dqm" whose definition and functions are explained in any manufacturer documentation concerning SDRAM memories and which will therefore be dealt with only in brief here.
Read operation
The time diagram relating to a read operation for an SDRAM is given in FIG. 1. This read operation depends on two programmable parameters referred to as "cas latency" and "burst length".
In the example in FIG. 1, the "cas latency" instruction corresponding to the latency time in read mode is equal to 3. This means that the data dq are read three cycles after the read instruction has been received. The "burst length" instruction is equal to 4, which means that four consecutive data are extracted from the same received address information. The dotted line 1 corresponds to the activation of the address (ad) as a "row" address by the ras signal (row address strobe) and the dotted line 2 corresponds to the activation of the address (ad) as a "column" address by the cas signal (column address strobe) with read instruction. The latency time corresponds to the time between the application of the "column" address (ad) and the data output. The dotted line 3 corresponds to the reading of the valid data dq, 3 clock cycles after the cas signal.
Write operation
The time diagram relating to a write operation for an SDRAM is given in FIG. 2. This operation depends on the "burst length" signal which represents the number of consecutive data which are written from the same address information. The dotted line 4 corresponds to the row addressing (ras). The dotted line 5 corresponds to the column addressing (cas) with the activation of the write instruction (we).
Again with reference to FIG. 1 and the read operations, the time Tac is the access time for the data after the clock rising edge corresponding to the last cycle as defined by the latency time, and Toh is the holding time for these data after the next clock rising edge (therefore corresponding to the latency time). When the operating frequency is high, the data dq which have been read remain valid for a short period of time, as represented by the unhatched "valid data" signal segment through which the dotted line 3 passes in FIG. 1. For example, for 100 MHz clock frequency and for times Tac and Toh of respectively 8.5 ns and 3 ns, the time for which the data which has been read remains valid and can therefore be acquired is: EQU 10 ns-8.5 ns+3 ns=4.5 ns
Acquisition of these data within this time interval requires that the clock of the circuit managing the SDRAM memory, which circuit will be referred to below as the controller, and the SDRAM memory's own clock be in phase. If this is not so, then it will not be possible for the data to be dealt with reliably.
If the controller is an integrated circuit, or part of an integrated circuit, the control, address and data signals sent to the SDRAM memory by this circuit, which are synchronized with the internal clock derived from the external clock signal received on the clock input of the circuit, will not generally be synchronized with the external clock signal directly received by the SDRAM memory, even though the signals sent to these two clock inputs are the same, as explained below.
FIG. 3 represents an SDRAM memory controller 6 which is connected to an SDRAM memory 7 by a link 8 for exchanging the control, address and data signals, according to the prior art.
The same clock H is sent to the input of the memory controller circuit 6 and to the input of the SDRAM memory 7. The controller receives this clock on its clock input and distributes it to the various circuits which need to be synchronized with this clock. In order for this to be done, the clock signal which is received needs to be "buffered" several times for a tree distribution, before being delivered to the circuits which exchange signals on the link with the SDRAM memory, as indicated in FIG. 3. Each buffer circuit creates a delay of a few nanoseconds, and an overall delay of the order of 5 to 10 nanoseconds can make this direct link 8 between the controller and the memory unreliable, because of the desynchronization between the clock H and the signals exchanged on this link.
Of course, the controller may use PLL circuits (phase locked loops). But such circuits increase the complexity and cost of producing ASICs. Delay lines may also be utilized, but there are known problems inherent with components of this type, their calibration needs to be perfect and fine adjustment is expensive.